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1 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches general description the fm3540/50/60 multiplexes the i-port input signals with two internal non-volatile registers that can be loaded through the serial port. the multiplexer is selected via the serial port and defaults to the i-port upon power-up. pull-up resistors are provided on the input port to accommodate connections to open drain outputs and to eliminate the need for external resistors. the device supports a choice of either 2.5v output or open drain outputs for easy interface to devices with different vdd levels. the serial port is an iic compatible slave only interface and supports both 100kbits and 400kbits modes of operation. the port is used to read the i-port, write data to the internal non-volatile block diagram june 2000 registers and select whether the i-port or one of the internal non- volatile registers is output to the y-port. the fm3540/50/60 is fabricated with an advanced cmos technology to achieve high density and low power. features extended operating voltage range 3.0v-5.5v iic compatible slave interface. esd performance: human body model > 2000v choice of 2.5v outputs or open-drain outputs ?2000 fairchild semiconductor international sopra soprb iic interface start/stop logic shift register slave address register comparator control logic mux3 mux2 non_mux_out y[4:0] i[4:0] iic read logic sda scl asel ovrd muxsel mxsb, mxsa mux1
2 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 sda 1 14 scl i0 2 13 vcc i1 3 12 y0 i2 4 11 y1 i3 5 10 y2 i4 6 9y3 gnd 7 8y4 scl 1 16 vcc sda 2 15 wp override# 3 14 non_mux_out i0 4 13 mux_sel i1 5 12 y0 i2 6 11 y1 i3 7 10 y2 gnd 8 9y3 scl 1 20 vcc sda 2 19 asel override# 3 18 wp i0 4 17 non_mux_out i1 5 16 mux_sel i2 6 15 y0 i3 7 14 y1 i4 8 13 y2 level 9 12 y3 gnd 10 11 y4 ordering code fm 35xx x x xx m so package option mt tssop package option c open collector output configuration s 2.5v output configuration blank default address - 1001110 a alternate address - 0110111 order number package number package description fm2540cm14 m14a 14-pin so fm3540cmt14 mtc14 14-pin tssop FM3550sm16 m16a 16-pin so FM3550smt16 mtc16 16-pin tssop fm3560m20 m20b 20-pin so fm3560mt20 mtc20 20-pin tssop for all other combinations, check with fairchild marketing/sales pin connection diagrams 14-pin packages fm3540 16-pin package FM3550 20-pin packages fm3560 pin description pin name description i[0:4] data inputs w/pullups (10k-40k) y[0:4] o/d data outputs scl serial port clock input (120k pullup) override# override input, sets all outputs to 0 wp write protect input non_mux_out non-multiplexed output mux_sel mux. select input level level select input asel address select input sda serial port data i/o (120k pullup)
3 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 functional description the FM3550/60 is block diagram is show in figure 1. the device has two primary functional modes of operation and an additional mode for programming the device. operational modes during standard operation the device will either pass an address to the y-port from the i-port or from an internally programmed value. at power up the device will default to passing the i-port value to the y-port. the i-port values are generated from the motherboard of the system and may be hardwired or driven by another device. pull- up resistors are provided on the device to accommodate this device being driven by open drain output drivers. the device expects standard cmos input signals. the level of the output signal is determined by the level input. if this input is connected to vss/ground, the output is at 2.5v on the multiplexed outputs (y0-y4). the non-multiplexed output is always at cmos levels. the level input, if left unconnected (it has an internal pullup), will cause the y0-y4 outputs to operate as open-drain outputs. the override# input, when set to 0, will cause all the outputs to be set to 0. the wp signal, if set to logic 1, will prevent data from being written to the non-volatile register. the mux_sel input, when set to logic 0, will select the data from the non-volatile register to drive on the y0-4 outputs. if set to logic 1, the data from the inputs are selected instead. the non_mux_out latch is transparent when the mux_sel signal is at logic 0, and will latch data when the mux_select is in a logic 1 state. output port: y0-y4 the output port is an open drain output to allow for easy connec- tion to devices running at different voltage levels. the port is always active and either passes the value on the i-port or the value in the serial output port register (sopr). changing the mux path is accomplished by writing to b7, b6 of the serial input port register. sopr-b7, b6 defaults to a value of "10" at power up and the default path is from the i-port through to the output port. the multiplexer only updates when an iic stop condition is observed. register description the FM3550/60 has 3 registers in total. these registers are made up of a combination of read only, write only and read write bits. the two registers are listed below. serial output port register a(sopra) address: 00h - a read/ write register that contains the new value to be written to output port-y and the multiplexer select bit. serial output port register b(soprb) address: 01h - a read/ write register that contains the new value to be written to output port-y and the multiplexer select bit. parallel input port register (pipr) address: 02h - a read only register that is loaded with the 5 bit value of the i-port. serial output port register (sopr) (address 000b and 001b) mxsb mxsa data field 0 0 i5 nmo i3 i2 i1 i0 b7 b6 b5 b4 b3 b2 b1 b0 b7-b6 - multiplexer select bits (mxsb,mxsa) 00 - multiplexer passes the sopr(a). 01 - multiplexer passer the sopr(b). 10 - multiplexer defaults to passing the i-port value. b5, b3-b0 - data field. new value to be output through the multiplexer. nmo - non multiplexed output from internal non-volatile bit parallel input port register (pipr) (address 002b) address field data field 0 0 0 i4 i3i2i1 i0 b7 b6 b5 b4 b3 b2 b1 b0 b7-b5 - address field. value is always 000 b4-b0 - data field. value is equal to the value on the i-port. the external port register captures the value on the i-port. data is latched into this register on the first clock after a start condition is seen. this insures that a valid value will always be in this register if it is read. this register is a read only register with respect to the iic port. over- mux_ non_ ride# sel mxsb mxsa mux_outputs mux_output 0 0 x x all 0's all 0's 0 1 x x mux_inputs latched nmo (see note 1) 1 0 1 0 mux_inputs latched nmo (see note 1) 1 0 0 0 from non- from non- volatile reg- volatile reg- ister (sopra) ister (sopra) 1 0 1 1 do not use this combination 1 0 0 1 from non- from non- volatile reg- volatile reg- ister (soprb) ister (soprb) 1 1 note 2 note 1 mux_inputs from non- volatile reg- ister (sopra or soprb) note 1: latched nmo state will be the value present on the nmo output at the time of the mux_sel input transitioning from logic 0 to logic 1 state. note 2: output depends on previously selected state of mxsb and mxsa bits written to device.
4 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 multiplexer logic the output multiplexer logic determines what value is actually output to the y-port. the value that is output is dependent upon b7- b6 of the sopra and soprb registers, as well as the external mux_sel and override# inputs. the is only one set of mxs bits in the sopra and soprb registers. regardless of whether one writes to sopra or soprb register for setting the mxs bits, the result is the same. these same bits appear in both the registers. if the mux_sel is logic 0 and ovrd is logic 1, then, if b7,b6 is ?0 then the value on the i-port is passed. when b7 is ?0?the value of the sopra register is passed on the next iic stop condition, and .when b7 is ?1?the value of the soprb register is passed on the next iic stop condition. if mux_sel is logic 1 and ovrd is logic 1, the input lines i0-4 are used to drive the outputs. the above table describes all the combinations. iic interface the iic interface is a standard slave interface. as a slave interface the device will not generate its own clock. data can be read from and written into the device. commands for reading and writing the registers are generated by the iic master. start and stop conditions if so desired only the sopra register can be read. this is accomplished by issuing a stop command after acknowledge bit for the first byte read. if no stop is issued, the device will output the registers in the above sequence. writing to the registers data is written to the sopr registers through the serial port interface. when a write request is received with the start address it is assumed that the intent is to write the sopr registers. the value placed in the least 6 significant bits of the register contain the new code to be placed in the sopr a/b registers. the value of the two most significant bits must contain the address of the destina- tion register sopra or soprb. the internal non-volatile latch takes about 10 ms to update its data. the new data is reflected on the outputs after the internal non-volatile latch is updated, if the corresponding select bits (mxsx, ovrd and mux_sel) are set to reflect the state of the non- volatile register register read sequence slave sopra soprb pipr s address r a register a register a register a p s 1001110 1 a 00bbbbbb a 00bbbbbb a 00bbbbbb a p register write sequence slave soprx s address w a register a s s 1001110 0 a xxbbbbbb a s xx = register selection bits (mxsb and mxsa) xx = 00 selects sopra, 01 selects soprb register write sequence using repeated start condition slave sopra slave soprx s address r a register a s address w a register a p s 1001110 1 a 00bbbbbb a s 1001110 0 a xxbbbbbb a p figure 4 the iic protocol uniquely defines start and stop conditions. a start condition is defined as a high to low transition of the sda signal while scl is high. a stop condition is defined as a low to high transition of the sda signal while scl is high. these are shown in figure 2. device addressing the device uses 7 bit iic addressing. the address has been defined as 1001 110 if the asel input is ??and 0110 111 if the asel input is ?? the address byte is the first byte of data sent after a start condition. this is the only address that this device will respond to. the device will not respond to the general call address 0000 000. reading from the registers data can be read from both of the internal registers. all reads are non-destructive and do not change the value in the register or the internal state of the device. when a start condition is received with a read request both registers can be read out in the following sequence. (1) sopra - serial output port register a (2) sporb - serial output port register b (3) pipr - port-i value sda scl start condition stop condition
5 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 absolute maximum ratings (note 1) supply voltage (v cc ) -0.5v to +6.5v dc input voltage (v i ) -0.5v to +6.5v output voltage (v o ) outputs 3-stated -0.5v to +6.5v outputs active (note 2) -0.5 to v cc +0.5v dc input diode current (i ik ) v i < 0v -50ma dc output diode current (iok) v o < 0v -50ma v o > vcc +50ma dc output source/sink current (i oh /i ol ) 50ma dc vcc or ground current per supply pin (i cc or ground) 100ma storage temperature range (t stg ) -65 c to +150 c recommended operating conditions (note 3) power supply 3.0v to 5.5v input voltage -0.3v to 5.5v output voltage (v o ) 0v to v cc output current i ol 3ma free air operating temperature(ta) -0 c to +70 c minimum input edge rate (d t /d v ) v in = 0.8v to 2.0v, vcc = 3.0v 10ns/v note 1: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits . the parametric values defined in the electrical characteristics table are not guaranteed at the absolute maximum ratings. the recommended operating conditions table will define the conditions for actual device operation. note 2: io absolute maximum rating must be observed. note 3: floating or unused pins (inputs or i/o s) must be held high or low. dc electrical characteristics (4.5v < v cc 5.5v) symbol parameter conditions v cc (v) min max units v ih high level input voltage 4.5 - 5.5 v cc x 0.7 v v il low level input voltage 4.5 - 5.5 v cc x 0.3 v v ol low level output voltage i ol = 100 a 4.5 - 5.5 0.2 v i ol = 3ma 0.4 i ir input leakage current v i =v il 5.5 -10 +10 a i cc quiescent supply current v i = v cc or gnd 4.5 - 5.5 300 975 a v cc (va i, v o) 3.6v dc electrical characteristics extended (3.0v v cc 5.5v) symbol parameter conditions vcc (v) min max units v ih high level input voltage 3.0 - 5.5 v cc x 0.7 v v il low level input voltage 3.0 - 5.5 v cc x 0.3 v v ol low level output voltage i ol = 100 a 3.0 - 5.5 0.2 v i ol = 3ma 0.4 v oh output high voltage fixed output mode, ('s' grade 3.0 - 5.5 2.3 2.5 v samples, or fm3560 with level input = logical 0 ) 1 ttl load, 50pf capacitance i ir input leakage current v i =v il 5.5 -10 +10 a i cc quiescent supply current v i = v cc or gnd 3.0 - 5.5 300 975 a v cc (v i, v o ) 3.6v
6 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 ac characteristics symbol parameter t a = 0 c to +70 c,c l = 30pf, r l = 500 ? units v cc = 5.0v 0.5v v cc = 3.3 0.3v min max min max t phl prop delay i to y 50 50 ns t plh prop delay i to y 50 50 ns t phl prop delay to y (from ovrd or mux_sel) 50 50 ns t plh prop delay to y (from ovrd or mux_sel) 50 50 ns iic ac characteristics symbol parameter t a = 0 c to +70 c,c l = 30pf, r l = 500 ? units 100khz 400khz min max min max f scl scl clock frequency 100 400 khz t 1 noise supression time constant 100 50 ns t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before a new 4.7 1.3 s transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 0.6 s t high clock high period 4.0 0.6 s t su:sta start condition setup time (for a 4.7 0.6 repeated start condition) t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1000 300 ns t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s capacitance symbol parameter conditions ta = +25 c typical units cin input capacitance (i4-i0) v i =0v or v cc , v cc =3.3 or 5.0 6 pf c i/o input/output capacitance (sda) v i =0v or v cc , v cc =3.3 or 5.0 7 pf c out output capacitance (y4-y0) 7 pf non-volatile memory characteristics parameter specification data retention 10 years minimum number of writes 1,000,000 cycles
7 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 molded small outline package (m) order number fm3560xm package number m20b x = c for open collector and x = s for 2.5v physical dimensions inches (millimeters) unless otherwise noted
8 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 molded small outline package (m) order number FM3550xm package number m16a x = c for open collector and x = s for 2.5v physical dimensions inches (millimeters) unless otherwise noted
9 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 molded small outline package (m) order number fm3540xm package number m14a x = c for open collector and x = s for 2.5v physical dimensions inches (millimeters) unless otherwise noted
10 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 order number fm3540xmt package number mtc14 x = c for open collector and x = s for 2.5v physical dimensions inches (millimeters) unless otherwise noted
11 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 order number FM3550xmt package number mtc16 x = c for open collector and x = s for 2.5v physical dimensions inches (millimeters) unless otherwise noted
12 www.fairchildsemi.com fm3540/50/60 4/5 bit multiplexed, 1 bit latched port with standard 2-wire bus interface and non-volatile latches www.fairchildsemi.com fm3540/50/60 rev. a.1 physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 order number fm3560mt package number mtc20

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